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Job Location | Bangalore, Noida, Hyderabad, Ahmedabad |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | IT - Software |
Functional Area | General / Other Software |
EmploymentType | Full-time |
2 to 15 years of experience in Verification Experience working of SV and UVM methodology and experience of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required, must have executed at-least 2 SoC Verification projects .Fluent in System Verilog HVL and hands-on on Verilog and VHDL. Hands on experience in developing source code with reasonable complexity.Hands on experience in developing feature list, testplan and formal verification strategies from scratch. Strong working experience of Formal Verification EDA tools Magellan, Jasper, IFV, Questa Formal. BE/BTECH,ME/MTECH is preferred ,
Keyskills :
uvmahbapbambaverificationeda toolssystem verilogsoc verificationworking experienceformal verificationedasocusbhvlpciemipijasperquestaverilog
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