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Chip Power Estimation Engineer

2.00 to 4.00 Years   Bangalore   22 Oct, 2021
Nvidia Corporation
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Hardware / Networking
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

NVIDIA is seeking a passionate, creative, and highly motivated engineer to work on architectural power estimation for the world s leading GPUs and SOCs. In this position, the responsibility includes development of advanced power models to estimate chip and board power under product driven use cases. You are expected to understand the high-level chip architecture, application use-cases, low power design techniques, process technology aspects which impact dynamic and leakage power, develop the estimation infrastructure, estimate power consumption under various scenarios. You will be working with architecture, design, synthesis, timing, circuit, and post silicon teams to accomplish your tasks.This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. Were united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.The GPU started out as an engine for simulating human imagination, conjuring up the amazing virtual worlds of video games and Hollywood films. Today, NVIDIA s GPU simulates human intelligence, running deep learning algorithms and acting as the brain of computers, robots, and self-driving cars that can perceive and understand the world. NVIDIA is increasingly known as the AI computing company. What you ll be doing:

  • Architecture, development and correlation of power estimation models/tools for NVIDIAs chips
  • Help architect and develop power models for use-cases, Idle power and IO power
  • Chip in to design the tools based on these models and their testing methodology/infrastructures
  • Correlate and Calibrate the power models using measured silicon data
  • Analyze and help decide the chip configuration and process technology options to optimize power/performance for NVIDIAs upcoming chips
  • Help study and contribute to Performance/Watt improvement ideas for NVIDIAs GPUs and SOCs
What we need to see:
  • B.Tech./M.Tech or equivalent experience and 2 years of experience related to Power / Performance estimation and optimization techniques
  • Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits
  • Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS)
  • Strong background in power estimation techniques, flows and algorithms
  • Good programming skills - Python preferred. Good skills with object-oriented programming and design
Ways to stand out from the crowd:
  • Exposure to lab setup including power measurement equipment such as scope/DAQ with ability to analyze board level power issues is a plus
  • Exposure to power analysis EDA tools such as PTPX/EPS
  • Good communication skills & desire to work as a great teammate
With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the most desirable employers in the world. We are an equal opportunity employer and value diversity at our company. We do not discriminate on the basis of race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.,

Keyskills :
estimationautocadtenderboqcustomer relationseda toolsboard levelvideo gamesdeep learningvirtual worldspower analysispower estimationchip architecturecommunication skillsoptimization strategiesedavlsiidleobjectoriented programming

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