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ENGR II, DESIGN LAYOUT TL

2.00 to 7.00 Years   Bangalore, Chennai, Hyderabad, Delhi   08 Nov, 2021
ON Semiconductor Technology India Private Limited
Job LocationBangalore, Chennai, Hyderabad, Delhi
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

* Requirements

  • 1 - 2 years of experience, B.E/B.Tech, M.S/M.Tech in Electrical Engineering with relevant courses in VLSI design.
  • Experience with Cadence and Mentor graphics EDA tools for a custom layout.
Preferred Qualifications
  • Good understanding of analogue basics of CMOS.
Responsibilities
  • Work on the custom layout of analogue circuit blocks in design with minimal guidance.
  • Preparation of floorplan of a block with attention to details on signal, and supply paths.
  • Able to run parasitic extractions, Design Rule Checks, Layout versus Schematic, Electrical Rule checks.
  • Documentation of layout work.
  • Engage regularly with circuit designers.
  • Good Knowledge of device characteristics and familiarity with the manufacturing of CMOS devices.
  • Good communication and debugging skills.
  • Insights into matching, short channel effects, parasitic minimization approaches are preferred.
  • Skill/Python scripting experience is an added advantage.
  • Exposure to image sensor designs.
, *
  • Bachelors or Masters degree

Keyskills :
layout versus schematiccontinuous improvement facilitationeda toolselectrical engineeringedavlsicmosertmsdesignsupplycheckscircuitgraphicsanaloguematchingscriptingdebuggingfloorplanmentor graphicscadence

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