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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | IT - Software |
Functional Area | General / Other Software |
EmploymentType | Full-time |
This position is located in Bangalore, India.
As a Design Engineer contributing to FPGA RTL team, you will be creating and verifying new Accelerated Functional Units (AFUs) that are part of a complete ingest, transform, and infer pipeline in the FPGAs. You will be developing and integrating components that are leading edge/pre - release technologies from multiple vendors and OEMs.
ResponsibilitiesPrimary responsibilities are to develop the FPGA RTL infrastructure to allow offload of compute - intensive algorithms on to FPGAs. This includes:
The following qualifications are required:
The following qualifications are highly desirable:
Using FPGAs for advanced real - time analytics of streaming data
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