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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.Derive the test plan based on the PHY protocol, device architecture and the applicationExecuting the tests based on the test planAnalyze the Test results and debug failuresWork with the Systems team and test for system inter-operability. Experience in using lab equipments such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc.. Familiarity with Verilog, Labview, pythonRequirements:B.Tech/M.Tech in ECE4 to 10 years of experience in Post Silicon ValidationGenuine interest in HardwareStrong fundamentals in ElectronicsGood Communication skillsWe re doing work that matters. Help us solve what others can t.,
Keyskills :
catia v5autocaddrawingweldingbomnetwork analyzerphytestslabviewverilogsiliconprotocoloptimizerarchitecturefundamentalscommunicationNoise Figure MeterSignal Generatorscadence