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Lead Design Engineer

2.00 to 7.00 Years   Bangalore   03 Nov, 2021
Cadence Design
Job LocationBangalore
EducationNot Mentioned
SalaryRs 2.0 Lakh/Yr
IndustryIT - Software
Functional AreaR&D / Product Design,General / Other Software
EmploymentTypeFull-time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

  • Hand-on work experience in ASIC/IP/Subsystem/SOC/PHY level Verification primarily in protocols PCIe / NVMe / USB /SATA
  • Extensive experience in developing Verification environment and methodologies using Verilog / System Verilog / UVM / OVM / e Specman based languages
  • Proficient in PCIe PHY based protocol checkers / assertions using Verilog / SVA
  • Knowledgeable in integrating Serial-link VIPs, Verilog Real modelling of analog behavior and debug in various Industry Simulation tools
  • Hands on in regression setup, Coverage / Metric analysis and Vplan are preferable
We re doing work that matters. Help us solve what others can t.,

Keyskills :
weldingprotocolsuvmregressionprotocolanalysissystem verilogovmdrawingcatia v5usbpciephyspecmanbomassertionssimulationverilogautocadcadence

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