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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | Service / Installation / Repair |
| EmploymentType | Full-time |
The position requires an energetic, proactive, self-starting person, who is able to lead and coordinate full chip DFT task and work closely with other DFT engineers to explore new methodologies. You must possess strong technical knowledge in the area of design-for-test (DFT).Design for Test Engineer to perform any of the following ASIC design tasks:- Develop best in class, highest quality DFT methodologies for all design teams in meeting all test requirements & silicon quality standards- Implement/design/validate all DFT RTL/IP, required by all designs.- Drive latest DFT tools to produces highest quality DFT RTL/IP.- Drive ATPG generation/validation.- Work with RTL design, test engineering teams to implement highest quality DFT implementation.- Verify chip design for all DFT requirements, this includes DFT functional verification, DFT coverage verification and static timing analysis.- Static Timing/Noise/Coupling Analysis for test modes at chip level.- Generating clear documentation & easy to use scripts to support DFT flows.- Evaluation of tools in the development of DFT flows.- Responsible for day to day coordination of DFT designactivity and resources, in meeting project schedules.- work with ATE test engineers to debug production test patternsCandidate must possess the following skills:- ASIC design & implementation experience with specific background in the areas of Design for Test, RTL design &verification, static timing analysis, tool flow methodology (in order of priority.-BSEE plus 10 years, or MSEE plus 8 years, experience.- Hands on experience with the following areas: Logic Bist, Memory Bist, Boundary Scan, AC JTAG, scan/ATPG design implementationDFT process/flow development experienceUnderstanding of static timing and crosstalk/noise analysis.Understanding of synthesis/timing closure concepts.Write and debug RTL in Verilog and/or VHDL.Strong scripting languages such as TCL, Perl and UNIX shell.- Hands on experience with following design tools:DFT: Tessent, DFT Compiler, LogicVision*, TetraMAX, Fastscan,,
Keyskills :
atpgdft scancore siliconstatic timing analysis rtl designchip design asic designdft co