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PCIe Lead Design Engineer

5.00 to 6.00 Years   Bangalore   19 Dec, 2021
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaEngineering Design / Construction
EmploymentTypeFull-time

Job Description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.osition Description:

  • RTL Design Engineer for PCIe IP development team.
  • Position is based in Bangalore.
  • The role would include design and support of the RTL of the PCIe Gen3/4/5 IP solution of Cadence.
  • The work involved will be working with the existing RTL, addition of new features into the RTL, ensuring various customer configurations are clean as part of verification regressions, supporting customers, ensuring design is clean for LINT and CDC design guidelines.
Position Requirements:
  • BE/BTech/ME/MTech - Electrical / Electronics / VLSI with 5 yrs of experience as a design and verification engineer, with a large portion of the recent work experience on RTL design and development.
  • RTL Design using Verilog is a must.
  • System Verilog experience and experience with UVM based environment usage / debugging is required.
  • AXI3/4/5 experience is HIGHLY desired.
  • PCIe Gen3/4/5 experience is highly desirable. Prior experience in RTL design and implementation of complex protocols is a must.
  • Prior experience in IP development teams would be an added advantage.
We re doing work that matters. Help us solve what others can t.,

Keyskills :
catia v5autocaddrawingweldingbomrtl designpcielintdesigndebugging

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