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Physical Design Engineer

4.00 to 0.00 Years   Bangalore   15 Oct, 2021
Infinera India Pvt Ltd
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryTelecom / ISP
Functional AreaEngineering Design / Construction
EmploymentTypeFull-time

Job Description

ASIC Physical Design Engineer

  • Your Key Responsibilities Would Include:
  • Perform physical implementation steps including floor planning, place and route, power/clock distribution for congestion analysis and timing closure at block level as well as full chip
  • Work with logic designers to drive feasibility studies and explore design trade-off for physical design closure
  • Perform technical evaluations of vendor, process nodes and IP and provide recommendations
  • Develop physical design methodologies and automation scripts for various implementation steps
  • Perform static timing analysis, create timing constraints and validation, critical path analysis and timing sign-offEducation & Experience Necessary For Success:
  • 4 years of experience in ASIC physical design flow and methodologies in 7nm, 16nm and 28nm process nodes
  • Has solid knowledge of full design cycle from RTL to GDSII and understanding of underlaying concepts of IC design, implementation flows and methodologies for deep submicron design
  • Experience with EDA Place & Route tools like ICC2 or Innovus or similar tools and Timing tools like Primetime or similar
  • Scripting experience in TCL, python or perl
  • Candidates must have a Bachelors Degree or higher in Electrical/Electronics and Communication/VLSI/Microelectronics with very good academics.
Infinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability. EEO Employer/Vet/DisabledInfinera is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, religion, color, national origin, sex, age, status as a protected veteran, or status as a qualified individual with disability. EEO Employer/Vet/Disabled.,

Keyskills :
timing closureverificationpath analysisdesign flowroutingstatic timing analysisic designphysical designfloor planningdrcplace route

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