Physical Design Engineer

Job Description

Job ID: JR*******Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HirePhysical Design EngineerJob DescriptionThe IPG IP Engineering Group is looking for energetic and passionate Mixed-Signal Validation Engineers to verify high speed, state of the art DDRPHY/HBMIO designs. Job role involves defining and implementing MSV verification methodology, TB architecture, validation tests and environment to verify DDRPHY/HBMIO. Candidates need to have extensive experience in defining MSV test plan, implementing TB components, integrating spice netlists and spef, coding sequences, checkers, assertions, coverage, and debugging MSV simulations. Candidates should have the ability to work effectively with both internal and external teams and stakeholders. Strong problem solving and communication skills are desired. Candidates should be good team players.QualificationsMinimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.M.S with 7 yrs to 11 yrsMinimum Qualifications:B.E/B.Tech with 7yrs to 11 yrs experience in mixed signal verification domain.Preferred Qualifications: M.S with 7 yrs to 11 yrs experience in mixed signal verification domain.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.Inside this Business GroupIP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR*******BangaloreIP Engineering Group (IPG), Job ID: JR0191835Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HirePhysical Design EngineerJob DescriptionThe IPG IP Engineering Group is looking for energetic and passionate Mixed-Signal Validation Engineers to verify high speed, state of the art DDRPHY/HBMIO designs. Job role involves defining and implementing MSV verification methodology, TB architecture, validation tests and environment to verify DDRPHY/HBMIO. Candidates need to have extensive experience in defining MSV test plan, implementing TB components, integrating spice netlists and spef, coding sequences, checkers, assertions, coverage, and debugging MSV simulations. Candidates should have the ability to work effectively with both internal and external teams and stakeholders. Strong problem solving and communication skills are desired. Candidates should be good team players.QualificationsMinimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.M.S with 7 yrs to 11 yrsMinimum Qualifications:B.E/B.Tech with 7yrs to 11 yrs experience in mixed signal verification domain.Preferred Qualifications: M.S with 7 yrs to 11 yrs experience in mixed signal verification domain.Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.Inside this Business GroupIP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0191835BangaloreIP Engineering Group (IPG),

Keyskills :
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