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RTL / Digital Design Engineers (RTL)

4.00 to 7.00 Years   Bangalore, Hyderabad   05 Nov, 2021
Job LocationBangalore, Hyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

RTL / Digital Design Engineers (RTL) Lead ASIC Verification Engineers [Ref:102] RTL / Digital Design Engineers (RTL) Job Function: RTL / Digital design engineers will design and implementation of SoC , Peripherals , Graphics , Modem , Bus and Network - on - chip cores. These candidates will understand and work on all aspects of the VLSI development cycle such as architecture , micro architecture , Synthesis / PD interaction and design convergence and actively work with various core , verification , and physical design teams across multiple sites. They will perform RTL design , simulation , synthesis , timing analysis , lint check , clock domain crossing check , conformal low power check , and formal verification. Qualification Requirements : 4 - 10 years of solid experience in digital front - end design Expertise in RTL coding in Verilog / VHDL / SV Familiarity with various bus protocols like AHB , AXI is highly desired Experience in low power design methodology and clock domain crossing designs Experience in Spyglass Lint / CDC checks and waiver creation Experience in formal verification with Cadence LEC Understanding of full RTL to GDS flow Experience in mobile Multimedia / Camera design is a plus DSP / ISP knowledge is a plus Working knowledge of timing closure is a plus Expertise in Perl , TCL language is a plus Expertise in post - Si debug is a plus Good documentation skills ability to create unit level test plans Education Requirements: Required : Bachelors in Computer Engineering , Computer Science , Electrical Engineering , and / or related field Preferred : Masters in Computer Engineering , Computer Science , Electrical Engineering , and / or related field Location: Hyderabad , India; Bangalore , India; Silicon Valley , CA; San Diego , CA; Dallas , TX and Austin , TX,

Keyskills :
cadencestatic timing analysisasicasic designdrcrtl designrtl codingdigital designtiming closurephysical designtiming analysiscomputer scienceasic verificationmobile multimediasystem integratorsformal verificationelectrical engineering

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