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Senior/Principal Physical Design Engineer

5.00 to 10.00 Years   Bangalore   27 Dec, 2021
EnSilica India Private Limited
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

We are looking for bright candidates who have an enthusiasm and aptitude for working in this vital part of our business.

The ideal candidate will have a strong academic record and 5-10 years experience in IC Physical Design (PD) using advanced digital ASIC development flows.

You will have a solid track-record and be familiar with the challenges of implementing complex ASIC/SoC designs from RTL to tapeout-ready GDSII, preferably in process nodes down towards 5nm.

The candidate should have customer and supplier-facing experience and excellent communication skills.

Key responsibilities

  • Take full-flow ownership of all stages of the digital RTL-to-GDSII implementation flow for complex block-level or full-chip ASIC designs.
  • Work closely with our customers and other EnSilica teams to deliver projects on-time and to the required performance and quality levels.
  • Setup, run, and maintain EDA tool flows, as needed, for each stage of the development flow.
  • Follow EnSilica s ISO Quality Management System requirements for implementation, reviews, and reporting.
  • Keep up to date with all aspects of advanced ASIC implementation methodology and best-practice to ensure that EnSilica s expertise and services are always current and appropriate for each customer project.

Key Skills / Background

  • 1st or 2.1 Electronics, Physics or relevant subject from a Tier 1 group University.
  • 5-10 years experience in industry with a strong track record in Physical Design gained across several successful ASIC projects, and at process nodes down to ~7nm.
  • Ability to quickly and efficiently solve problems, working both independently and with support from colleagues, our suppliers, and our customers where needed.
  • Extensive hands-on experience with either Synopsys ICC1/2 or Cadence Innovus for block-level and/or full-chip physical design, preferably down to ~7nm FF.
  • RTL synthesis using Design Compiler or Genus, including DFT/scan-insertion.
  • Power-management implementation using UPF/CPF, including verification and power estimation.
  • Timing closure and STA, including constraint development and verification.
  • IR-drop/EM modelling, analysis and verification.
  • Setup, use, and verification of RC extraction flows.
  • Ability to setup, run, and debug DRC/LVS/ERC/DFM using at least one of the main EDA tool sets.

Desirable skills

  • Team leadership or technical management.
  • Experience in foundry tapeout.
  • ASIC package development and package/die co-design.
  • Foundry, Packaging, and IP supplier engagement and management.

Personal Skills

  • Ability to take full ownership of a task from initial assignment through to successful completion and sign-off
  • Quality-driven approach
  • Excellent communication and interpersonal skills
  • Self-motivated and adaptable
  • Take ownership of problems
  • Strong/Creative problem-solving skills
  • Good team player
,

Keyskills :
floor planningdrcroutingverificationintegrated development environmentsquality management systemrc extractiontiming closurephysical designproblem solvingpersonal skillsdesign compilerteam leadershippower managementmanagement systemqualit

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