Senior SOC Physical design Engineer

Job Description

Job ID: JR0191161Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSenior SOC Physical design EngineerJob DescriptionWe are an end-to-end design team, based in Bangalore part of Intel Labs. In this position, you will be responsible for the complete physical/back-end design convergence of complex SOC partitions starting from Synthesis till Tape-out. Along with the partition ownership you would be responsible for enhancing/customizing the PD flow & methodology based on the project needs. Your responsibilities will include the following: Working closely with the Design and Micro-Arch team in studying and analyzing the micro-arch specifications. Develop timing constraints and provide feedback based on RTL synthesis. Own IP block level floor planning, CTS and P&R optimizations to meet design specs. Verifying and ensuring that Area/Power/Performance specifications are met. Verify design for all physical design verification flows which include STA, FEV, IR drop, Noise, Low power checks and DRC&LVS Understand Intel physical design flows and debug/enhance the methodology as per project needs.QualificationsYou should possess a Masters degree in EE with at least 6 years of experience or a Bachelors degree in EE with at least 8 years of experience in VLSI physical design. Additional qualifications include: Knowledge of microelectronic designs, semiconductor device physics, CMOS process and physical layout. Good understanding of complete Physical design flow. Hands-on experience in converging complex blocks from RTL to GDSII (>500K instances) with embedded macros and low power implementation. Experience with PCIE or LPDDR phy integration is an add-on. Tape out experience with good understanding of latest process nodes DRCs (10nm, 7m/5nm). Experience in automation for design methodology and flow development. Strong debugging skills is must and should come up with technical solutions independently. Experience in logic synthesis, timing constraint development, floorplan, power plan, CTS, routing & timing closure and DRC & LVS closure. Experience in backend verification flows like STA, FEV, IR-drop analysis and low power verification. Good hands-on knowledge on EDA tools like Synopsys FC/DC-ICC2, Primetime, Spyglass, Cadence LEC, Ansys Redhawk and CalibreDrv/ICWEBV2. Good knowledge in scripting languages like Tcl &Shell (csh/tcsh/bash). Hands-on Experience in developing utilities in TCL/TK. Familiarity with hardware description language such as Verilog or System Verilog. Must be a good team player. Efficient in working with cross functional/geo teams with strong communication and leader ship skills.Inside this Business GroupIntel Labs is the companys world-class, industry leading research organization, responsible for driving Intels technology pipeline and creating new opportunities. The mission of Intel Labs is to deliver breakthrough technologies to fuel Intels growth. This includes identifying and exploring compelling new technologies and high risk opportunities ahead of business unit investment and demonstrating first-to-market technologies and innovative new usages for computing technology. Intel Labs engages the leading thinkers in academia and industry in addition to partnering closely with Intel business units.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0191161BangaloreIntel Labs,

Keyskills :
floor planningdrcroutingverificationhardware description languageeda toolstiming closurephysical designlogic synthesisbehavioral trainingdesign verificationsemiconductor devicephyedatcl