Senior Timing Sign-off Lead

Job Description

Job ID: JR*******Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSenior Timing Sign-off LeadJob DescriptionAs an integral part of Intel, we are establishing Intel Foundry Services (IFS), a fully vertical, standalone foundry business. IFS will be a world-class foundry business and major provider of US and European-based capacity to serve customers globally. Intel Foundry Services will be differentiated from other Foundry offerings with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe - available for customers globally - and a world-class IP portfolio that customers can chose from including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP, along with ARM and RISC-V ecosystem IPs. IFS will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages. This business unit is completely dedicated to the success of its customers with full P and L responsibilities. This model will ensure that our foundry customers products will receive our utmost focus in terms of service, technology enablement and capacity commitments. IFS is already engaged with customers today starting with our existing foundry offerings and we are expanding imminently to include our most advanced technologies, which are optimized for cutting-edge performance, making them ideal for high-performance applications. The timing sign-off leads responsibilities include Definition/Development of constraints for SOC Sign-off, setting up Timing Analysis Environment, driving timing convergence through influence of APR, Producing timing indicators to track the execution progress and final tape-out quality Sign-off . He / She should have in-depth experience in Primetime or equivalent tool-based Timing Analysis and should be an expert in developing SDC constraints, setting up Fullchip or subsystem level timing environment, Automating the Timing Execution/Indicator Extraction. He/She should have solid understanding of SOC Clocking Methodology, Understanding of requirements for Clock Domain Crossing, Clock Balancing across SOC partitions, Subsystem Level Logical/Physical Partitioning, implication of partitioning on overall Design Convergence. In addition, She/he must be able to influence RTL, APR execution and floor planning.Qualifications12+ Years of relevant Experience After a Bachelor or Master of Engineering degree in Electrical/ Electronic/VLSI Engineering or related field.Must have led at least 2 SOCs in capacity of SOC Sign-off lead especially on Sub 7nm projects.Solid Expertise in Primetime or Similar timing tools and good understanding of overall ASIC Physical Design/DFT, Tools and implication on Timing ConvergenceMust have in-depth understanding of relevant areas of Library / Memory / Other collaterals and dependencies on STAMust understand Ultra Submicron issues, Variation aware/Aging Aware Design Sign-offMust understand CTS/Other clock Distribution methodologies well.Teamwork / flexibility / ability to thrive in a chaotic environment are very importantInside this Business GroupAs the worlds largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore s Law to bring smart, connected devices to every person on EarthLegal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.,

Keyskills :
continuous improvement facilitationsupply chaintiming analysisconnected devicesclock distributionprocess developmentbehavioral trainingsemiconductor process