SoC Timing Lead

Job Description

Job ID: JR*******Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireSoC Timing LeadJob Description As an SoC Timing Lead, you will be part of the design team working on the next generation Xeon server product SOCs. This will be a fast-paced dynamic environment where you will lead a high performance design team towards convergence of timing across the entire SoC. Responsible for performing sub Full chip level and full chip level hierarchical timing analysis and convergence for complex multi-million gates Server SOC. Responsible for generating and verifying sub full chip level and full chip level implementation/Sign-off timing constraints for functional modes and other modes like DFT. Responsible for working closely with the clocking team to generate clock balancing guidelines and timing fixes considering all modes all corners and sign-off the design for Tape-out. Expectations include developing and defining methodologies to ensure the highest possible Silicon quality, overseeing the development of a system of timing indicators that enables the physical team to operate efficiently and ensuring high-quality timing models. Expert level knowledge of Primetime and associated timing model build flows is required. This role requires strong partnership between the overall physical design manager, timing team manager, Layout integration lead, partition leads and other technical leads to drive execution. Strong communicated skills, deep knowledge of the physical design project life cycle and a strong commitment to planning and executing to the projects high-level schedule are a must.QualificationsQualifications: BS in Electrical or Computer Engineering with 12+ years experience or MS in Electrical or Computer Engineering with 10+ years experience in Synthesis, Timing methodologies and flow development. Expertise and in-depth knowledge of industry standard EDA tools Prime time, Fusion Compiler, ICC as well as proficiency in scripting languages, such as, Python, Perl, and Tcl. Knowledge of circuits, SPICE simulations, and/or transistor level STA. Demonstrate a deep understanding of Static Timing Analysis, timing constraints generation and management, and timing convergence. You are capable of analysing and converging cross-talk delay, noise glitch, process variation, and electrical/manufacturing rules and the modelling of these effects in deep-sub micron processes required. Experience in generating, handling and validating timing and SI models to reduce the memory footprint and Sign-off run times and simultaneously ensuring required accuracy at various stages of design cycle You have demonstrated a capability of driving hardware architecture and hands-on skills in RTL, Logic design for timing closure desired. Knowledge in physical design and optimization e.g. placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, and implementing them through ECOs. Preferably experience in 7 nm, 10 nm and 14nm Implementation flows Latch based design and CPU implementation background would be a plus. Excellent verbal and written communication skills.Inside this Business GroupXeon and Networking Engineering (XNE) focuses on the development and integration of XEON and Networking SOCs and critical IPs sustain Intels Xeon and 5G networking roadmap.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR*******BangaloreXeon Engineering Group (XEG),

Keyskills :
project life cyclestatic timing analysiseda toolslife cyclelogic designmusic makingtiming closurephysical designtiming analysissystem integrators