Sr Engineer - RTL and DFT

Job Description

*Title: Sr Engineer Physical DesignAbout GLOBALFOUNDRIESGLOBALFOUNDRIES is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Investment Company. For more information, visit www.globalfoundries.com.Introduction As an RTL and DFT Engineer in the team, you will be working independently on RTL Architecture, Implementation, DFT methodologies and post Silicon Debug / Analysis for the high-speed mixed signal designs. Being automotive would require field test, BIST and advanced fault models to meet the test goals and quality. You will be responsible for resolving challenges for digital as well as analog DFT to bring down test time and test cost for the product. Expected to interact with the global product and test engineering teams. Experience with owning chip level DFT architecture, execution and Post Silicon debug / analysis. Job Responsibilities

• RTL Design and integration for System on Chip (SOC) from initial specification till tapeout and beyond.
• Fluency in coding RTL in system Verilog and doing validation in tools like Cadence Verilog XL, NCSim, Cadence Simvision, Cadence XCelium, Synopsis Verdi, Synopsis VCSMX, Cadence Genus, Synopsis DC.
• Signing off RTL, timing constraints, CDC and work with different functions like verification, synthesis, etc. to get to a production quality Silicon.
• Documenting the SOC design and micro-architecture for usage by other SOC functions
• Specific Knowledge/Skills
• Experience >3 Years in IP/SOC RTL design with successful delivery of production quality IP/SOCs
• Hands-on experience on Chip Assembly, RTL Design, IP Integration, RTL signoff tools and CDC/RDC.
• Experiences in RTL design flow from Specification/Micro-architecture definition to design and verification and Implementation.
• Familiarity with Computer architecture: knowledge of microprocessors, bus protocols preferred.
• Knowledge of Clocking, System modes, Power management, debug, interconnect, safety, security and other architectures

Understanding of DFT architectures like JTAG, Scan Compression Techniques (XOR, Adaptive, OP-MISR etc.), scan chain insertion and verification. Must have experience generating scan patterns and coverage statistics for various fault models like stuck at(Nominal and VBOX), IDDQ, Transition faults, JTAG BSDL, pattern generation for Memories (E-fuse etc.). Experience debugging tester failures of scan patterns, diagnosis and pattern re-generation. Understanding generation of functional patterns for ATE Knowledge of at least any one of an industry standard DFT tools (Cadence Modus, Synopsys Tetramax, Mentor Tessent Tools, etc) Design experience in MBIST / LBIST is an added advantage. Experience with automotive SOCs (field test, advanced fault models,) is an advantage. Good understanding of constraints development for Physical Design Implementation / Static Timing Analysis. In depth knowledge and hands on experience in scan insertion, ATPG, coverage analysis, Transition delay test coverage analysis In depth knowledge and hands on experience in MBIST insertion and Memory test validation.Expertise in test mode timing constraints definition, knowledge in providing timing fixes/corrective actions for timing violations. Experience in RTL and Gate level simulations of scan and MBIST test vectors. Knowledge of equivalence check, DFT DRC rules both in RTL lint tool (like spyglass) and ATPG tool like (TetraMax). Working experience in Synopsis TetraMax/DFTMax and Cadence Encounter Test is a plus. , *Required Qualifications:

• Bachelor or masters degree in Electrical and Electronics engineering.
• Minimum of 3-5 years of experience RTL with DFT in digital/analog IP circuit design, layout, and timing experience in block and full chip level.
• Language Fluency Fluent in English Language written & verbal.
• Must have transistor level electrical circuit design understanding.
• Must be able to interpret electrical design specifications.
• Knowledge of chip design tools and flows including synthesis, timing, verification, and place-and-route tools.
• Knowledge of AIX/NFS, Linux, Shell, Tcl, Perl
• Must have good technical verbal and written communication skills and ability to work with cross functional teams is necessary.
• Candidates who are self-driven and have worked in a global team environment with a successful track record of on-time high quality IP design creation.
• Be able to collaborate with program and technical design leads on multiple concurrent projects.
• Should have excellent problem-solving skills, written & oral communication, teaming & interpersonal skills
• Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Preferred Qualifications:

• Experience with TCL / Perl is preferred.
• Experience in RTL coding in system verilog is strongly preferred.
• Understanding of IC design with Analog circuits and it s design cycles is an added advantage.
• Effective communication skills to interact with all stakeholders.
• Ability to work in an international team, dynamic environment.
• Ability to learn and adapt to new tools and methodologies.
• Ability to do multi-tasking & work on several high-priority designs in parallel.
• Excellent problem-solving skills.
• Excellent communication and teamwork skills and good English is required.
• The candidate should have good people skills to work closely with the systems, analog, layout and test team.
• Must be highly focused and remain committed to obtaining closure on project goals.

Keyskills :
continuous improvement facilitationic designrtl designrtl codingfield testchip designdesign flowmemory testmixed signalpeople skillstest coverage