Standard Cell Library Lead Design Engineer

Job Description

Job ID: JR0188743Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireStandard Cell Library Lead Design EngineerJob DescriptionIn this position, you will lead and participate in the design, development, validation, and delivery of standard cell libraries using leading process technologies for use in the design of Intels next-generation SoCs and microprocessors. Responsibilities include, but are not limited to: - Design and implementation of the combinatorial, clock, power management, and sequential circuits for Intels newest process technologies. - Parasitic extraction and circuit optimization for power/performance/robustness/density. - Library characterization for timing, noise, power, and variation models (non-linear delay models; composite current source models, parametric on-chip variation models). - Reliability verification of standard cells covering ERC, EM, SH, FinFet self-heating. APL characterization and modeling. - Developing functional models behavioral Verilog, power udp Verilog and fault models. - Development of automation for library modeling, validation, quality checking, performance, and reliability verification. - The library build, validation, QA, release, and support. - Technically lead a team of engineers, debug problems, remove execution roadblocks, detailed planning of execution/releases, and work on strategic initiatives for future technologiesQualificationsYou must possess a minimum of Masters degree in the field of electronics engineering. Specialization or experience in VLSI is preferred. A minimum of 7+ years of relevant experience in standard cell library design or associated domains. The successful candidate must possess excellent written and verbal communication skills, strong customer/result orientation and the ability to work with external and internal partners in a flexible manner. Additional/Desired Qualifications: - Experience in digital circuit design, including CMOS combinatorial logic and sequential element design and layout. Good understanding of device physics and FinFet characteristics. - Experience using industry-standard design automation tools in one or more of the areas: circuit simulation, std cell characterization, synthesis, place and route, physical design verification and reliability verification. - Experience in scripting (TCL, Perl, Python, ML) for design automation - Experience working in the Linux environment and its development tools - Experience in EDA tool/flow/methodology, product and IP developments are strongly preferred. - Good engineering acumen and analytical skills. Quick learner with debugging skills.Inside this Business GroupIP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0188743BangaloreIP Engineering Group (IPG),

Keyskills :
catia v5autocaddrawingweldingbomdigital circuit designstandard cellcircuit designphysical designpower managementautomation toolscommercial models