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| Job Location | Bangalore, Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Synthesis & STA engineers will perform RTL Synthesis to achieve the best Performance/Power/Area of the designs, DFT insertions that include MBIST and SCAN, setup Timing Constraints for functional and Test Modes, and Validation. These candidates will create Power Intent for the designs and verify power intent on RTL, run static Low- Power checks on gate level netlists, Verify Logic Equivalency Checks between RTL to Gates and Gates to Gates, setup signoff Static Timing Analysis and ECO flows and achieve timing closure working with the Design/DFT/PD teams, run Power Analysis and estimate power at RTL level, run Sign off Power Analysis on the P&R data, support the DV team to enable gate level simulations with SDF and UPF aware simulations, and support functional eco rollout with automated ECO flows.
Qualification Requirements :Keyskills :
static timing analysisrtl designsystem verilogtiming closureasic synthesissynopsys toolspower analysistiming analysiscomputer sciencesandftrtlstaecoupfperlscanasic