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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Recruitment Services |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Verification EngineerAbout Company :It is a fast- growing Technology company that specializes in the creation of Intellectual Properties, Frameworks and Solutions for the Networking, Storage, Consumer, Enterprise and Device Mobility markets. The team leverages decades of experience in delivering high- quality, production- proven, high- speed serial interconnects Silicon IP cores and custom and standard form factor hardware boards to leading customers worldwide. With a highly motivated engineering team, dedicated integration support, Flexible business models, strong industry presence through strategic alliances and key partnership.Location : BangaloreExperience : 3 12 YearsFunction : OthersVacancy : 2Be responsible for a participate in and lead CPU and Graphics Cache Sub- System function verification domain.Be part of a team of designers and verification engineers, working closely with other team members to implement and verify the functionality of a given design element within the context of the block, chip and overall system as well as to design features for the next generation in RTL.Must have good knowledge on the verification flows. Excellent hands- on debug skills and problem solving attitude.Experience of working in complex test- bench/ model in Verilog, System Verilog or SystemCExperience of working on Functional Verification, SoC Verification, EmulationGood in programming : System Verilog, PLI/ DPI interface, C/ C , PERL/ Shell script, assembly language, OVM/ UVM Methodology knowledge and experienceMust have good communication skills and the ability to work in a team environment. Preferably having experience in architecture such as x86 or ARM domain based SOCs,
Keyskills :
verification uvm design failureanalysis ip shellscript systemverilog problemsolving socverification assemblylanguage communicationskills arm soc x86 trategicalliances functionalverification it cpu dpi