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Job Location | Hyderabad |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Consumer Durables / Electronics |
Functional Area | General / Other Software,Testing |
EmploymentType | Full-time |
Roles and Responsibilities Hello,Hope you are doing Well!! JOB DESCRIPTION:: Do Coverage Closure Own and debug failures in simulation to root-cause problems Co-work with Design / Sw teams and develop reusable verification environments, Own cross functional Debug and drive issues to closure. Own and execute Gate Sims Mentor Junior Team MembersQUALIFICATIONS:: Expert in Front End Verification using SV-UVM based test benches. Should have developed SV -UVM test benches for multiple projects Should have Developed SV / C based test cases and participated in complete verification cycle including coverage closure and Gate Sims Good understanding of integrating C with SV UVM test benches Able to define verification methodologies and quality metrics for verification projects Should have expertise in defining Test plans for Block, IP, Sub-System , SoC verification Good debugging and problem solving skills. Expertise with ASIC simulation, regressions and coverage tracking tools Ability to multi-task and meet aggressive goals Experience in defining and closing coverage requirements. Experience with scripting languages like Perl, Python Experience of working with PCIe , AXI, AHB, SERDES systems Experience of writing assertions and working with Formal verification tools Setup Automated regressions environment and in general automate repetitive verification tasks to enhance productivity Experience of Co-working with SW and C Model development teams to integrate their deliverables into verification test bench BE/M.Tech in Electronics Engineering with 6+ years of experience,
Keyskills :
ambadebuggingfeatureslanguagesoopsfront endtest casesproblem solvingmodel developmentformal verificationelectronics engineeringsocuvmaxiahbperlstatements of work sow