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| Job Location | Hyderabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Design Verification Engineers (DV) Job Function: Design verification engineers will likely have experience in functional or formal design verification. These candidates are expected to know the essential technical languages , disciplines , and methodologies that are generally tacked to this type of position. Qualification Requirements : At least 4 years of experience in ASIC verification including: Verification methodology using System Verilog , SVA , OVM / UVM , Vera , or VMM Experience in writing feature based test plans and implementing such test plans using one of the methodologies listed above Experience running regressions , debugging test failures and achieving test plan targets Knowledge in hardware description languages (HDL) such as Verilog , SystemVerilog and VHDL Analytic and debugging skills Strong knowledge of digital design Understanding of Object Oriented Programming (OOP) concepts Experience with Gate Level Simulation , Low Power Verification , Formal Verification are preferred Familiar with C / C++ , Perl , Tcl Education Requirements: Required : Bachelors in Computer Engineering , Computer Science , Electrical Engineering , and / or related field Preferred : Masters in Computer Engineering , Computer Science , Electrical Engineering , and / or related field Location: Hyderabad , India; Bangalore , India; Silicon Valley , CA; San Diego , CA; Dallas , TX and Austin , TX,
Keyskills :
verificationuvmdesignfailure analysisgate level simulationobject oriented programmingsystem verilogdigital designcomputer scienceasic verificationformal verificationdesign verificationelectrical engineeringsantclovmvmm