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Layout (Analog / Standardcell) Engineers / Sr. Engineer / MTS / SMTS

2.00 to 6.00 Years   Hyderabad   30 Oct, 2021
Job LocationHyderabad
EducationNot Mentioned
SalaryNot Disclosed
IndustryMedia / Dotcom / Entertainment
Functional AreaEmbedded / System Software,General / Other Software
EmploymentTypeFull-time

Job Description

Layout (Analog / Standardcell) Engineers / Sr. Engineer / MTS / SMTS Advanced understanding of Deep submicron effects and mitigation, Good exposure on Cadence and Mentor Graphics tools. Good understanding of CMOS layouts and process technology in 28nm and below technologies. Hand on experience in FinFet Technology will be added advantage. Good understanding of ASIC physical design flow: LEF generation, Place & Route. Good understanding standard cell abutment rules, memory & IO layout design and requirements, EM and IR considerations, DFM, etc. Scripting skills for layout automation is advantage. Excellent written and verbal communication skills in interactions with customers, and internal development teams. Candidate will be responsible for doing hands on full custom analog/ mixed signal / RF layouts on cutting edge technology and will be layout lead. Bachelors or above on Electronics, Communications or Microelectronics Engineering. Strong skills on CMOS analog / mixed signal / RF Layout. Good understanding of devices and process technology. Expertise on matching, parasitic reduction, ESD, DFM etc. Proficiency in use of EDA tools for full custom layout and post- layout verification DRC / LVS / DFM etc. Experience on full chip layout & verification, Data converters, high speed Phys & PM layouts are preferable. Knowledge of perl / shell / skill scripting Qualification: B.Tech / M.Tech or equivalent from a reputed University. Experience: 2 - 8 years of relevant experience. Location: Bangalore/ Hyderabad APPLY NOW,

Keyskills :
drcmtsperledalvsesddfmverbal communicationlayout verificationmixed signalphysical designstandard celllayout designmentor graphicseda tools

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