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| Job Location | Mumbai City |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Education / Training |
| Functional Area | Network / System AdministrationWeb / Mobile Technologies |
| EmploymentType | Full-time |
Responsibilities Determine logical verification strategy and approach for a particular ASIC, SoC or any complex system Develop behavioral models in C++ and/ or SystemC Write the verification test plan Specify, develop, or enhance the verification environment, checkers and/ or bus functional models Develop regressable, self- checking test suites Debug the design and isolate failures Requirements 4+ years experience in logical verification of ASICs and systems Experience with C, C++ and SystemC Experience in Verilog and VHDL is a plus Experience in developing C/ C++/ SystemC based behavioral models on Linux, Solaris and Windows platforms Demonstrated skills in applying reusability to the design and implementation of Verification suites Have successfully defined, development, and used multiple verification environments, using a variety of methodologies and techniques Experience in transferring verification environments and test suites to others, and supporting their use Experience in writing test plans for ASICs / SoCs including embedded processors Experience in implementing test suites and isolating failures Experience with embedded processors, DSPs, and/ or standard busses is a plus Experience with Software Co- simulation is a plus Excellent software engineering skills, including programming style, configuration and release management, and documentation Ability to handle a team independently and identify the best solution among best practices, based on personal experience,
Keyskills :
costreduction inspection kanban marketing safety testsuites testplanning releasemanagement softwareengineering soc bus vhdl linux design windows solaris writing sic