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Principal Design Engineer

7.00 to 10.00 Years   Pune   22 May, 2020
Job LocationPune
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaService / Installation / Repair
EmploymentTypeFull-time

Job Description

  • 7 years of design verification experience
  • BS (or higher) in EE/Computer Engineering
  • Experience in mentoring junior engineer
  • Excellent knowledge of computer architecture and design verification fundamentals
  • Some experience with Verilog and popular EDA simulation, System Verilog assertions and testbench methodologies
  • Experience in developing complex test bench in SystemVerilog using OVM/UVM methodology
  • Exposure to scripting languages like Perl, Unix shell or similar languages
  • Some experience with assembly language programming required
  • Excellent written and oral communication skills necessary
  • Candidate must be self-motivated and capable of working independently or as part of a team
  • Must have exp. of mentoring/ leading a small team.
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Keyskills :
lighting estimation 3dmodelling ahu auditing systemverilog assemblylanguage oralcommunication designverification communicationskills computerarchitecture eda perl unix design verilog scripting mentoring simulation adence

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