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Senior Engineer/Staff Engineer DFT

8.00 to 10.00 Years   Pune   30 May, 2020
Job LocationPune
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

  • Experienced in various aspects of DFT SCAN insertion, ATPG & JTAG, BSCAN. Test generation, coverage improvement, post - silicon debug.
  • Hands on experience on DFT industry standard tools from Cadence, Mentor Graphics used for SCAN insertion, MBIST implementation and validation is must have requirement.
  • Working with soc/post silicon team to improve/ address low scan coverage and implement methodology to enhance scan coverage is expectation.
  • Qualifications Candidate should possess a Bachelor s degree with 8 - 15 years industry experience in VLSI, Electronics, Electrical, Computer Engineering or Computer Science (from reputed colleges like IIT/NIT, global universities).
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Keyskills :
safety commissioning site inspection troubleshooting scaninsertion computerscience dft soc vlsi atpg jtag scan science silicon graphics validation engineering entorgraphics cadence

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