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Staff Engineer - Design Verification

10.00 to 0.00 Years   Pune   09 Jul, 2020
Marvell India Pvt Ltd
Job LocationPune
EducationNot Mentioned
SalaryNot Disclosed
IndustryConsumer Durables / Electronics
Functional AreaService / Installation / Repair
EmploymentTypeFull-time

Job Description

  • Architect and implement simulation test bench in UVM.
  • Develop and execute test-plans for verifying correctness and performance of the design.
  • Own and debug failures in simulation to root-cause problems
  • Closely work with logic designers of the block being verified for test plan development, execution, debug, coverage closure and gate level simulations
Requirements
  • Strong background in Soc verification methodology and test bench development using HVL such as Verilog, System Verilog, UVM and C/C.
  • Strong verification skills, understanding of methodology (object oriented programming, white-box/black-box, directed/random testing, coverage, gate-level simulations).
  • Knowledge of Unix/Linux environment and scripting (shell/Perl/Python) is a plus.
  • Demonstrates good analysis and problem-solving skills.
  • Must have the ability to multi-task in a fast paced environment.
  • Must have effective interpersonal and teamwork skills and excellent communication skills.
  • Ability to interface internally and externally with all levels of the organization.
  • Participate in problem solving and quality improvement activities.
  • BS in CS/EE with 10 years of relevant experience.
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Keyskills :
linuxandroidautomationframeworkopen sourcesystem verilogcloud computingproblem solvingsoc verificationapplication supportquality improvementintellectual propertycorporate citizenshiparmsocuvmcpuhvl

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