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Veification Engineer

3.00 to 5.00 Years   Pune   22 Dec, 2020
Job LocationPune
EducationNot Mentioned
SalaryRs 2.0 - 5 Lakh/Yr
IndustryIT - Hardware / Networking
Functional AreaEmbedded / System Software
EmploymentTypeFull-time

Job Description

Skill Set: Design VerificationJob Title: Senior Engineer/Verification Lead/Sr.Verification engineer/Formal Verification/AMD Project Experience/Technical managerExperience working of SV and UVM methodology and experience of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required, Must have executed at-least 2 SoC Verification projects. At-least 2 years of experience in handling team of 5 to 10 engineers.Minimum 6 years experience in ASIC/FPGA verification, including verification of complex ASICs at chip-level Expertise in SystemVerilog/UVMKnowledge of C and/or Python preferredNetworking protocol (i.e. Ethernet, OTN) and/or FEC experience is a mustBasic knowledge of SerDes and ADC/DAC a plusExpertise in independently building SV/UVM test benchesExpertise in developing test cases and test plansFunctional coverage, code coverage closure experience a mustGate sims and debugging.Experience in lab validation and bring up activities is a plusFluent in System Verilog HVL and hands-on on Verilog and VHDL.Hands on experience in developing source code with reasonable complexity.Hands on experience in developing feature list, testplan and formal verification stratagies from scratch.Strong working experience of Formal Verification EDA tools Magellan, Jasper, IFV, Questa FormalMust have 2+ years of AMD project experience and familiar with their working environment and operations SoC DVExpertise Verification and Testbenches (SOC/IP)System Verilog/UVM/CPP hands on experiencePCIE/AXI protocols (X86 cores knowledge is a plus point)*Incumbent will be responsible for Functioning with clients, technical teams for securing & executing concurrent objectives;*Incumbent will be responsible for SubSystem level verification of Ethernet MAC + PCS Layers and Storage protocol SAS SPL-4 for Expander Device using UVM.*Incumbent will have to drive verification IP development of various protocols such as MIPI CSI-2, DSI, D-PHY using SystemVerilog & UVM/OVM. IP/Block level verification of complex ASIC/SoC/FPGA using constrained random and coverage driven methodology.If interested, please send ur resumes to aparna.n@agasthyaaplabs.comcontact: 7794067150 .

Keyskills :
ethernetusbmipiapbambaahbpcle

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