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* About GLOBAL FOUNDRIES GLOBAL FOUNDRIES is the world s first full-service semiconductor foundry with a truly global footprint. Launched in March 2009, the company has quickly achieved scale as one...
ppap productdevelopment apqp inspection documentation designrulechecking layoutversusschematic edatools chipdesign standardcell circuitdesign designverification esignrulecheckingdrcVery strong Physical Design experience required Excellent Communication skills mandatory Skills Required : Knowledge of Physical design and verification at SOC Level. Hands on experience with Synops...
drc routing verification ip physicaldesign communicationskills soc sta design communication PhysicalVerification lo planning dracula ClockTreeSynthesis PlaceRoute TimingClosure DesignRuleChecking PrimetPhysical Design Engineer Responsible for and own all aspects of physical design and physical verification effort at a block level. Worked on Netlist to GDSII at block level for multiple tapeouts Exp...
planning drc routing verification ip physicaldesign physicalverification design ClockTreeSynthesis PhysicalVerification TimingClosure DesignRuleChecking Primetime lo perf mance PlaceRoute LayoutVersusLead Engineer - Analog Mixed Signal and RF Layout 6+yrs Experience; Full Chip Layout of Analog PHYs , SerDes , I / Os , Data Converters , PLL , Baseband Circuit ,...
java customerrelations linux automation mixedsignal rf os ertms serdes circuit baseband BiCMOS PowerManagement SerDes CMOS VCO DesignRuleChecking LayoutVersusSchematic haseLockedLoopDirector Physical Design @ Bangalore Semiconductor (MNC) 16+ yrs PD, PnR, floorplan, Timing, Synthesis. Handling a team of PD engineers and good communication. ,...
physicaldesign pnr design timing floorplan engineers semiconductor ClockTreeSynthesis PhysicalVerification TimingClosure DesignRuleChecking Primetime LayoutVersusSchematic Floorplanning ParasiticExtraction Redhawk TravelSystems GlobalDistSynthesis & STA Job description Education : BTech in EC/ EE/ Telecommunication is must. MS/ MTech VLSI is preferred Location : Bangalore No. of positions : 2 Desired Skills: Minimum 2+ year of experi...
physicaldesign dft rtl sta upf vlsi design voltage synthesis communication telecommunication ClockTreeSynthesis PhysicalVerification TimingClosure DesignRuleChecking Primetime LayoutVersusSchematic Floorplanning adence PlaceRoute1. Prior experience in Product Engineering or a related field is preferred 2. Exceptional Communication Skills (written and verbal) are Required as this is a Customer Facing position 3. Prior experien...
bts troubleshooting site bscs leansixsigma productlifecycle solidstatephysics designrulechecking managecomplexprojects tatementsofworksow designrulecheckingdrcPhysical Design Engineer Responsible for and own all aspects of physical design and physical verification effort at a block level. Worked on Netlist to GDSII at block level for multiple tapeouts Exp...
planning drc routing verification ip physicaldesign physicalverification design ClockTreeSynthesis PhysicalVerification TimingClosure DesignRuleChecking Primetime lo perf mance PlaceRoute LayoutVersusWafer Space is looking for smart and enterprising Physical Designer Engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Alw...
cadence synopsys apache eda fusion physicaldesign edge wafer design engineers ClockTreeSynthesis PhysicalVerification TimingClosure DesignRuleChecking Primetime LayoutVersusSchematic laceRoute Flo planniPosition Title: IP Circuit Design and Layout Development Engineer Work Area: Foundry IP Development Location : Bangalore Summary of Role :
Position Title: IP Efuse Macro / Circuit Design and Layout Development Engineer Work Area: Foundry IP Development Location : Bangalore Summary of Role :
Position Title: IP Efuse Macro / Circuit Design and Layout Development Engineer Work Area: Foundry IP Development Location : Bangalore Summary of Role : <...
designrulechecking edatools chipdesign standardcell technicaldesign electricaldesign projectmanagement designverification scheduledevelopment esignrulecheckingdrcWafer Space is looking for smart and enterprising Physical Designer Engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Alw...
cadence synopsys apache eda fusion physicaldesign edge wafer design engineers ClockTreeSynthesis PhysicalVerification TimingClosure DesignRuleChecking Primetime LayoutVersusSchematic laceRoute Flo planniPosition Title: IP Circuit Design and Layout Development Engineer Work Area: Foundry IP Development Location : Bangalore Summary of Role :
M.Tech in Vlsi design from a good school Analog/ Mixed signal design experience with SerDes background. ,...
graphicdesign cad mechanical sales tender mixedsignaldesign vlsidesign mixedsignal signaldesign vlsi ertms design serdes BiCMOS PowerManagement SerDes CMOS VCO DesignRuleChecking haseLockedLoopVery strong Physical Design experience required Excellent Communication skills mandatory Skills Required : Knowledge of Physical design and verification at SOC Level. Hands on experience with Synops...
drc routing verification ip physicaldesign communicationskills soc sta design communication PhysicalVerification lo planning dracula ClockTreeSynthesis PlaceRoute TimingClosure DesignRuleChecking PrimetVery strong Physical Design experience required Excellent Communication skills mandatory Skills Required : Knowledge of Physical design and verification at SOC Level. Hands on experience with Synops...
drc routing verification ip physicaldesign communicationskills soc sta design communication PhysicalVerification lo planning dracula ClockTreeSynthesis PlaceRoute TimingClosure DesignRuleChecking PrimetConducting audit as allocated and scheduled by the HO within stipulated time as per audit SOP. Physical Verification of stock stored in godown, inventory available in godown, comments on infrastructur...
stockaudit physicalverification pan warehouse inventory australasia infrastructure Hercules ParasiticExtraction ClockTreeSynthesis Virtuoso DesignRuleChecking RCExtraction LayoutVersusSchematic Floorplanning VATRegistration TaxDeductedatSoSynthesis & STA Job description Education : BTech in EC/ EE/ Telecommunication is must. MS/ MTech VLSI is preferred Location : Bangalore No. of positions : 2 Desired Skills: Minimum 2+ year of ...
physicaldesign dft rtl upf vlsi design cadence voltage education synthesis communication telecommunication ClockTreeSynthesis PhysicalVerification TimingClosure DesignRuleChecking Primetime Layout laceRouteVery strong Physical Design experience required Excellent Communication skills mandatory Skills Required : Knowledge of Physical design and verification at SOC Level. Hands on experience with Synops...
drc routing verification ip physicaldesign communicationskills soc sta design communication PhysicalVerification lo planning dracula ClockTreeSynthesis PlaceRoute TimingClosure DesignRuleChecking Primet
SoC Interns for HSPE group. Responsibilities may be quite diverse of a technical nature. Job assignments are usually for the summer or for short periods during breaks from school. Collage Interns - VL...
soc vlsi collage TimingClosure StaticTimingAnalysis RTLDesign Primetime Processors AMBAAHB PhysicalDesign FunctionalVerification RTLCoding DesignRuleChecking ClockTreeSynthesis NCSim Pen Abstraction Clay Canvas owpowerDesignResponsibilities may be quite diverse of a technical nature. U.S. experience and education requirements will vary significantly depending on the unique needs of the job. Job assignments are usually fo...
soc vlsi collage education TimingClosure StaticTimingAnalysis RTLDesign Primetime Processors AMBAAHB PhysicalDesign FunctionalVerification RTLCoding DesignRuleChecking ClockTreeSynthesis NCSim Pen Abstraction Clay owpowerDesignVery strong Physical Design experience required Excellent Communication skills mandatory Skills Required : Knowledge of Physical design and verification at SOC Level. Hands on experience with Synops...
drc routing verification ip physicaldesign communicationskills soc sta design communication PhysicalVerification lo planning dracula ClockTreeSynthesis PlaceRoute TimingClosure DesignRuleChecking PrimetWafer Space is looking for smart and enterprising Physical Designer Engineers to come join us and get an opportunity to do some cutting edge work and also work in a great environment where work is Alw...
cadence synopsys apache eda fusion physicaldesign edge wafer design engineers ClockTreeSynthesis PhysicalVerification TimingClosure DesignRuleChecking Primetime LayoutVersusSchematic laceRoute Flo planniSynthesis & STA Job description Education : BTech in EC/ EE/ Telecommunication is must. MS/ MTech VLSI is preferred Location : Bangalore No. of positions : 2 Desired Skills: Minimum 2+ year of ...
physicaldesign dft rtl upf vlsi design cadence voltage education synthesis communication telecommunication ClockTreeSynthesis PhysicalVerification TimingClosure DesignRuleChecking Primetime Layout laceRouteLead Engineer - Analog Mixed Signal and RF Layout 6+yrs Experience; Full Chip Layout of Analog PHYs , SerDes , I / Os , Data Converters , PLL , Baseband Circuit ,...
javacustomerrelationslinuxautomationmixedsignalertmsserdescircuitbasebandBiCMOSPowerManagementSerDesCMOSVCODesignRuleCheckingLayoutVersusSchematichaseLockedLoopVery strong Physical Design experience required Excellent Communication skills mandatory Skills Required : Knowledge of Physical design and verification at SOC Level. Hands on experience with Synops...
drcroutingverificationphysicaldesigncommunicationskillssocstadesigncommunicationPhysicalVerificationplanningdraculaClockTreeSynthesisPlaceRouteTimingClosureDesignRuleCheckingPrimetPerson having 3-5 yrs. experience in library characterization and Validation. Knowhow of: .lib, liberty, lef, gds, red hawk.Familiarity with Synopsys liberty format is needed. Good Q/A and debugging F...
edatoolsedagdsredlibrarylibertydebuggingcharacterizationTimingClosurePhysicalDesignPhysicalVerificationPrimetimeParasiticExtractionStaticTimingAnalysisDesignRuleCheckingowpowerDesignPlaceEmbedded, Embedded Developer Embedded Linux OS concepts Hands on experience in CAN Protocol, Strong knowledge on Communication protocols (CAN, MOST, LIN, FlexRay) Walk in Interview 29 July 2019 to 1...
protocolsdirectfbmicrocontrollerprotocolopenembeddedembeddedommunicationprotocolsdesignrulecheckingconditionalaccessembeddedcphysicalverificationvlsidesignembeddedsystemsembeddedlinuxboardbring-upsettopboxSupport STCO effort in compute-in-memory, in support of client collateral creation and eventual co-development opportunities ,...
physicaldesigndesigncollateralClockTreeSynthesisPhysicalVerificationTimingClosureDesignRuleCheckingPrimetimeLayoutVersusSchematiclaceRouteVery strong Physical Design experience required Excellent Communication skills mandatory Skills Required : Knowledge of Physical design and verification at SOC Level. Hands on experience with Synops...
drcroutingverificationphysicaldesigncommunicationskillssocstadesigncommunicationPhysicalVerificationplanningdraculaClockTreeSynthesisPlaceRouteTimingClosureDesignRuleCheckingPrimetVery strong Physical Design experience required Excellent Communication skills mandatory Skills Required : Knowledge of Physical design and verification at SOC Level. Hands on experience with Synops...
drcroutingverificationphysicaldesigncommunicationskillssocstadesigncommunicationPhysicalVerificationplanningdraculaClockTreeSynthesisPlaceRouteTimingClosureDesignRuleCheckingPrimetExperience with different physical verification checks like DRC, LVS, Antenna, ERC, PERC, ESD etc. Experience in sign- off PDV tools like PDK Concepts, SVRF, Calibre. Experience in PnR tools like ICC/...
verificationuvmdesignfailureanalysisphysicalverificationdrclvsesdpnrpdkVirtuosoRCExtractionhecksantennaHerculesParasiticExtractionClockTreeSynthesisPlaceRouteDesignRuleCheckingVery strong Physical Design experience required Excellent Communication skills mandatory Skills Required : Knowledge of Physical design and verification at SOC Level. Hands on experience with Synops...
drcroutingverificationphysicaldesigncommunicationskillssocstadesigncommunicationPhysicalVerificationplanningdraculaClockTreeSynthesisPlaceRouteTimingClosureDesignRuleCheckingPrimet© 2019 Hireejobs All Rights Reserved