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| Job Location | Vishakhapatnam |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Cement / Building Material |
| Functional Area | Sales / BD |
| EmploymentType | Full-time |
MSEE or PhD in EE with 10+ years of hands- on/ management experience in SoC/ ASIC/ digital designLocation: VizagJoin GigaCom/ Moschip and manage a world- class Digital Design Team in providing high performance digital and mixed mode designs for leading high speed serial communications. Candidate will have opportunities to design high performance transceivers along with critical functions, including:Analog- to- digital converters (ADC) Digital- to- analog converters (DAC) Phase- Locked Loop (PLL) Adaptive equalizers, finite- impulse response (FIR) filter, and decision- feedback equalizer (DFE) Serializer- Deserializer (Serdes) Clock and data recovery (CDR) circuits Timing critical circuits Roles and Responsibilities: Manager along with team members participate in architecture, partitioning, implementation, design review, physical design, verification and silicon validation. Qualified candidates should have strong RTL/ digital design fundamentals with hands on design experience managing a team designing high performance digital logic in the following areas at a minimum:Good understanding of Verilog(RTL), Digital design principles, Timing Constraints Front End Design and Implementation steps including Micro- Architecture, RTL Coding, constraints generation/ verification/ review, Lint check, CDC check, DC Synthesis and PT Static Timing Analysis Experience with low- power designs Experience with high- speed design techniques Ability to develop clear and concise Engineering documents Ability to work with internal Verification Team for verifying the IP and Validation Team for bring- up. FPGA knowledge a Plus Experience in Clock and Data Recovery, Equalization, Adaptation algorithms, LMS algorithms, PLL modeling is a plus.Fluent in various CAD tools for Digital Design from RTL coding to Physical Design.,
Keyskills :
graphic designcad mechanicalsales tenderfront end design static timing analysisfront end