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| Job Location | Ahmedabad |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Experience in FPGA domain Hands on experience in design, timing closure, validation Must have worked on Altera FPGAs Hands on knowledge of verilog Good to have knowledge of AMBA protocols - AXI, AHB, APB. Experience in Synthesis / Understanding of timing concepts for ASIC is required. Experience in design of DDR / USB / PCIe controller or such complex protocols is a plus. Hands on experience in Multi Clock designs, Asynchronous interface is a must. Experience on tools utilized in all phases of ASIC development such as Lint, CDC, Simulation etc. is required. Knowledge of low power concepts and experience is a plus ,
Keyskills :
domaintoolsusbprotocolsdesignindesigninterfacesdivconceptskedon