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ATPG - VLSI Automatic Test Pattern Generation-Vlsi Engineer

1.00 to 3.00 Years   Bangalore   14 Sep, 2020
Wipro Limited
Job LocationBangalore
EducationNot Mentioned
SalaryNot Disclosed
IndustryIT - Software
Functional AreaGeneral / Other Software
EmploymentTypeFull-time

Job Description

Key skills required for the job are:

  • ATPG - VLSI Automatic Test Pattern Generation-L2 (Mandatory)
  • VLSI Memory BIST and Boundary SCAN-L1
DFT synthesisGood knowledge of Hierarchical scan synthesis with :o Scan segmentationso Test modelsHandle module level scan insertion.Handle device scan insertion with multiple clock domains.ATPGAble to do Block/ Device level pattern generation and simulations.Scan interleaved with memory bist patterns gen and validation.Device level transition delay testing with multiple clocks, handling exceptions.Able to do Sequential ATPG with RAMs and latches, coverage analysis.Path Delay tests, delay coverage analysis.Excellent knowledge on usage of ATPG tool.-Able to do Silicon debug and diagnosticsDelay tests using PLL, silicon debug and diagnostics.BISTGood knowledge of On-chip scans compression or bist techniques and test time reduction.Memory BIST integration in SoC and verification, selecting the optimal mem.Minimum work experience:1 - 3 YearsResponsible for development, support, maintenance,Implementation and Testing of complex components of an ASIC/SOC/FPGA/Board. Work on problems of relatively complex scope and apply own judgement. Responsible for the circuit design, circuit debugging, Design entryusing HDL, Integration, Simulation,schematic entry,layout & verification of complex components.Works as a fully contributing team member, under broad supervision / guidance. Requires solid knowledge of at least one design area. May guide new members in the team to help them scale up faster.,

Keyskills :
vlsisystem verilogverilogvhdlscan insertioncircuit designscale updftsochdlatpgbistscanramstestsdesignclockstestingpatterndigital electronics

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