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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Engineering Design / Construction |
| EmploymentType | Full-time |
In a fast-paced leading-edge design environment with endless possibilities of innovation and learning , you will be responsible for enabling design flows and methodology primarily in RTL2GDSII implementation and design sign-off areas such as Timing verification, EM/IR and Layout Verification. This is a great opportunity to join a team of talented individuals working directly with internal and external PDK and design teams who are in constant endeavor to improve design power, performance and area metrics (PPA) along with continuous focus to improve overall cycle time (TAT). The key skillsets need to include expertise in one or more areas of: o Floor planning with industry standard tools. o Multiple Power Domain implementation using standard Power Formats. o Place and Route and clock tree synthesis with industry standard tools. o Post-Route flows using well-formulated recipes for best in class power & performance o Performance verification ( Timing ) , Extraction, EM/IR and Physical verification. The responsibilities in this role expects the candidate to engage closely with : o Tool vendors, PDK teams, design teams and design automation teams to ensure and resolve design & convergence challenges, by formulating suitable implementation recipes with a focus on PPA & TAT optimizations. o Resolve tool/flow issues and drive improvements and innovation in design convergence through deployment of next-gen capabilities The ideal candidate should exhibit behavioral traits that indicate: o Self-motivator with strong problem-solving skills o Strong leadership skills with ability to mentor junior engineers. o Excellent interpersonal skills, including written and verbal communication. o Ability to work as part of a team and collaborate in a high-paced atmosphere. o Ability to provide technical direction to the team & influence design flows and methodology.QualificationsMtech/Btech Engineering Degree in field of Electrical, Electronics, Computer Science with 7-15 yrs of relevant RTL2GDS experience Demonstrated capability in methodology development and design enablement of complex multi-million gate designs, in areas of Synthesis, Floor-planning, Power-planning, Placement, CTS & Routing is a must Expertise and in-depth knowledge of industry standard EDA tools (Synthesis, Floorplanning, P&R) and ASIC design flow is required Multi-voltage scenarios design handling knowledge is expected. Knowledge of Sign-off flows such as Timing Verification, EM/IR , Layout Verification and ESD sign-off is an added advantage. Proficiency in scripting language, viz., Perl & Tcl would be required.,
Keyskills :
autocadcadauto caddraftingdrawingclock tree synthesiscontinuous improvement facilitationeda toolsasic designdesign flowfloor planningproblem solvingcomputer science