| Hyderabad Jobs |
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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Recruitment Services |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
4 - 8Years Job Location : Bangalore Deliver SOC level resimulated test pattern for ATE for the mentioned IPs. Here are the expertize required in the candidate Verification expert (Mostly Verilog , some System Verilog knowledge will be of advantage). Cadence NCSIM simulation tool. ATE pattern generation , re - simulation and pattern sign - off knowledge. Candidate will be using Lantiq test bench and will be introduced to TOPS Flow{internal tool} for test pattern generation and re - simulation.,
Keyskills :
pattern oodcommunication sign workingknowledge