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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Cement / Building Material |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
DFT Engineer MosChip Posted 1 week ago Qualification: Bachelors or Masters (Computer/ Electronics Engineering)Experience: 2- 5 YrsLocation: BangaloreCore Description: Responsible for SCAN, MBIST, JTAG, Vector generation and Verification and ATE post- silicon debug for complex 28nm and 22nm SoC.Mandatory Skills: 1) Experience in Scan insertion Compression, Pattern Generation and Validation.2) Expereince in Boundary scan, LBIST, MBIST, JTAG and Low Power DFT atChip level and IP level3)Tools: Fastscan/ TestKompress / DFTCompiler/ DFTMax/ DFTAdvisor/ TetraMax.Desired Skills: 1) In depth knowledge and hands on experience in scan insertion, MBIST insertion and Memory Validation, ATPG, coverage analysis, Transition delay test coverage analysis.2) Understand ATPG failures, debug or resolve DRC issues, Chain trace issues, Debug and Fix gate level Pattern simulation issues, both No- Timing and Timing simulation.3) Knowledge of IDDQ constraints generation and validation and silicon bring up and debug.4) Expertise in scripting languages like PERL, Shell etc.,
Keyskills :
atpg dft scan silicon boundaryscan testcoverage scaninsertion ip drc perl jtag trace timing pattern analysis boundary scripting validation vect