| Hyderabad Jobs |
| Banglore Jobs |
| Chennai Jobs |
| Delhi Jobs |
| Ahmedabad Jobs |
| Mumbai Jobs |
| Pune Jobs |
| Vijayawada Jobs |
| Gurgaon Jobs |
| Noida Jobs |
| Hyderabad Jobs |
| Banglore Jobs |
| Chennai Jobs |
| Delhi Jobs |
| Ahmedabad Jobs |
| Mumbai Jobs |
| Pune Jobs |
| Vijayawada Jobs |
| Gurgaon Jobs |
| Noida Jobs |
| Oil & Gas Jobs |
| Banking Jobs |
| Construction Jobs |
| Top Management Jobs |
| IT - Software Jobs |
| Medical Healthcare Jobs |
| Purchase / Logistics Jobs |
| Sales |
| Ajax Jobs |
| Designing Jobs |
| ASP .NET Jobs |
| Java Jobs |
| MySQL Jobs |
| Sap hr Jobs |
| Software Testing Jobs |
| Html Jobs |
| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Service / Installation / Repair |
| EmploymentType | Full-time |
Develops and supports design for test (DFT) structures. Determines design for test approaches and develops DFT architecture. Designs and verifies DFT structures for memories (MBIST), digital and analog circuitry. Performs scan synthesis. Creates, simulates and verifies automatic generated test patterns (ATPG). Creates functional tests and corresponding test patterns. Knows about failure mechanisms in silicon production and creates test algorithms. Supports silicon bring up of test patterns. Performs diagnosis of test patterns on silicon and optimizes test time.Qualifications Candidate should possess a Masters Degree in Electrical/Computer Engineering with 2-5 years of experience working in the domain of DFT engineering. Candidate should have a complete understanding of DFT concepts and flow (Scan/ATPG/Memory BIST/ B-Scan). Should be familiar with scan insertion, ATPG, scan compression, stuck-at, and at-speed scan testing. Experience in analyzing ATPG fault coverage gaps and identifying design and/or ATPG flow solutions. Experience in setting up SCAN/ATPG flows at IP/SubSystem/Partition level and debugging RTL issues that block scan coverage is highly desired along with the ability to run MBIST flows at an applicable hierarchical level. Hands-on experience with Industry-standard tools: Synopsys Spyglass DFT and Mentor Tessent ATPG, as well as GLS simulations with/without timing. Able to root-cause and resolve scan pattern simulation failures involving scan init, timing, cell/array modeling, etc. using standard simulation tools such as VCS, NCVerilog. Ability to generate patterns and run GLS flows and provide patterns to manufacturing is a plus. Knowledge of IEEE1149, 1687, 1500 is a must. Able to do scripting in Perl and Tcl. Silicon bring-up, debug, and validation of DFT features on ATE. ,
Keyskills :
atpgdftscancoresiliconcontinuous improvement facilitationscan insertioncommercial modelsbehavioral trainingrtlglsvcsperlips