Firmware Integration & Validation Lead

Job Description

Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireFirmware Integration & Validation LeadJob DescriptionReviews system validation environment and test suites. Uses and applies emulation and platform level tools and techniques to ensure performance to spec. Responsible for the development of debug methodologies for triage, isolation/root causing issues found during validation. Requires broad understanding of multiple system areas and requires interfaces with Architecture, Design, and Presilicon Validation teams in improving postsilicon test content and providing feedback for future ondie debug features. Understand Program requirements, Silicon / Hardware Internals , Mapping it to FW requirements. Domain areas in focus -Memory Controller -different memory model DDR, LPDDR, South Complex HSIO, IO configuration knowledge like PCIe, SPI, eSPI, USB etc North Complex technologies like Over Clocking, Caching, Power States, Graphics, Display etc, Patching flows for microcode and other silicon IPs. Creates, defines and develops system validation environment both Pre/Post Si debug capabilities. Work with different stakeholders, represent the team in different forums, get technical understanding of deliverables and drive effective integration and release plan. Need to work with different firmware teams to generate BKMs for seamless integration. Review, provide inputs ensuring test case traceability-coverage on PRDs, Design doc, UCIS, Corner case and customer use case scenarios. Uses and applies emulation and platform level tools and techniques to ensure performance to spec. Develop broad understanding of multiple system areas and requires interfacing with Architecture, Design, and Pre-silicon Validation teams in improving post-silicon test content and providing feedback for future on die debug features. Continuously monitor/drive test content quality/coverage enhancement based on escape analysis, specs, use case , customer scenarios. Support triage, isolation, root-causing, debug on sightings filed driving them to closure with offline and required execution via active participation/driving task forces across geos with inter-disciplinary teams based on need. Support in measuring validation metrics, gathering/ensuring data is meeting Quality release criteria needs. Ownership of FW component debug flows, debug, resolution, closure of must fix identified issues based on program milestone. Support debug engineers as required for issue replication, first level debugging capability on Payload failure detection, possible root-causes, inputs on must fixes to debug on-time to meet Program imperatives. Power On debugging using PythonSV and handling dungeon mode work-life for silicon bring-up. Integration of various IP Firmware to generate Stable Silicon Operations and feature enablement. Review all Technical details, supporting data/logs availability in filed sightings/defects for faster resolutions. Ensure all invalid bugs are filtered - Noise filtration - only genuine bugs are assigned to dev teams. Support development in verifying engineering/test binaries as needed. Understand different integration points of the firmware and release all collaterals for the External communication with clear POR configuration details with any deviation. Drive sync with multiple different IP FW teams across geos and get solutions integrated in the Official release. Define clear entry and exit criteria for sub systems for Integration and Release. Participate and contribute to Code reviews, excellent technical and problem solving skills. Single POC for assigned Platform and ability to work with different stakeholders in autonomy catering to vibrant needs spread across Geos. Establish validation requirements and ensure coverage of functional/non-functional requirements. Adapt, innovate and participate in technical assessment and be part of technical readiness for future programs. Work closely with architects for escape analysis data, PDT for retrospective data, ensure learnings are implemented in next programs. Drive Escape analysis process for Server programs.Qualifications Bachelors/Masters in Engineering in Electronics/Electrical/Computer Science/Embedded systems engineering with at least 8+ years of Prior experience in hands on FW Integration, validation, debug or experience of embedded systems testing with knowledge in releasing software to wider audience with proper documentation and organized formats. Software architecture design and test content development skills. Working knowledge in the software engineering development process project life cycle,BIOS architecture. Experience in Firmware API integration, validation Experience of Memory controller or Memory PHY and DDR memory protocols Experience with presilicon simulation verification or postsilicon verification UEFI Core BIOS for IA Silicon Product enabling Tiano and EDKII architecture on IA Implementation and ability to influence changes into industry specifications System BIOS Flow design and knowledge of OS dependencies on System Firmware Clear understanding of x86 architecture and bus protocols such as PCIE PSS LPC LPSS Audio SATA USB and DMI Knowledge of Windows OS and Linux kernel a plus Knowledge and working experience with logic analyzers, oscilloscopes, protocol analyzers, in-target probes and Lauterbach - Desired. Excellent programming knowledge in C, Assembly and Python/Scripting languages - Desired. A team player with good organizational and planning, leading skills, excellent verbal, analytical and presentation skills. Experience in Firmware integration, validation and debug on Intel Server platforms will be an added advantage.Inside this Business GroupIntel Architecture, Graphics, and Software (IAGS) brings Intels technical strategy to life. We have embraced the new reality of competing at a product and solution level not just a transistor one. We take pride in reshaping the status quo and thinking exponentially to achieve whats never been done before. Weve also built a culture of continuous learning and persistent leadership that provides opportunities to practice until perfection and filter ambitious ideas into execution.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0188301BangaloreIntel Architecture, Graphics, and Software,

Keyskills :
project life cycleuse casewindows oslife cyclelinux kernelpilot projectsproblem solvingembedded systemsworking experiencesystem integratorscontent development