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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Requirements: This role includes RTL design , verification , FPGA partitioning and implementation , and lab based bringup of the SoC on FPGAs. Recent FPGA experience including implementation , synthesis (Synplify) , timing closure (Vivado / ISE). Ability to architect , implement and verify modules for FPGA interconnect. Proficient in Verilog , Perl , and Make Both simulation based verification and lab based debug skills on FPGAs. Experience with a source control system , such as Perforce. Must be familiar with both Linux and Windows environments Hands on with lab FPGA debug methodologies , such as ChipScope , Identify or others. Hands on experience with lab debug equipment , such as oscilloscopes and logic analyzers. Educational Qualification BS / MS EE , EC , or CS Notice Period: 3 - 4week,
Keyskills :
socrtliseperlfpgalinuxdesignwindowsverilogimingclosurecontrolperfsynplifysynthesis