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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | Application Programming / Maintenance |
| EmploymentType | Full-time |
Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HireFull Chip Timing EngineerJob DescriptionJob Requirement: In this position, you will be responsible for all aspects of STA & timing closure activities of Intels SoCs in lower technology nodes. Your tasks will include but not limited to:Design & Architecture understanding, Interaction with FE/DFT/Verification teams, Clocking, Constraints development, ACIO Timing, Understanding on synchronous & asynchronous paths, Clock domain crossing issues, Understanding and debugging extraction issues, Deciding timing signoff modes & corners, Design margins, Hierarchical timing including IO budgeting for partitions, Drive the designs to timing closure, interacting/supporting synthesis and APR team during timing closure cycle, timing ECOs, Timing model build, Timing signoff & quality checks. You will also be part of debug/troubleshoots for a wide variety of tasks up to and including difficult/critical design issues and proactive intervention, as required.QualificationsQualification: Education: B.Tech. or M.Tech. in Electrical/Electronics Engineering with 4+ years of experience. Preference: Masters Degree in Electrical/Electronics Engineering with VLSI/microelectronics specialization, with 4+ years of experience in STA.Key Skills: - In-depth knowledge & hands-on experience with the overall silicon implementation flows and methodologies such as STA, Synthesis, Clocking is required. Good understanding & exposure of overall Timing closure cycle in SoC. - Good scripting skills in TCL/Perl/Shell. Expertise in STA signoff tools (PT/ETS). - Skill in Synopsys tools (PT/DC) & exposure to ICC will be an added advantage. - Solid understanding of the process and design interactions as they relate to target frequency and interaction with timing paths and resulting leakage and power trade-offs. - Solid technical and good communication skills.Inside this Business GroupThe Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.,
Keyskills :
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