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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Consumer Durables / Electronics |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Hiring : ASICDesign RTL-SOC-IP( Experience 4- 10 yrs )Location : BangaloreCompany : US Based Product Companyshare resume to shiva@cambio.co.inMULTIPLE Positions ranging from Junior to Lead Engineer.Sound experience in RTL Design is REQUIRED ranging from4to10Years. The selected candidate will have the following responsibilities: Block levelRTL(Verilog or System Verilog) design frommicro-architecturelevel specifications.Implementation ofLow powerlogic, targeting power, performance, area, and timing goals.Linting, CDC, LECand preferablyLow Powercheck tools to implement design and check design quality Work with Design Verification team on block and top-level functional/gate level verification and code coverage, including Power aware debug.,
Keyskills :
rtl designcode coverage design verificationrtl cdcdesign timingresume performanceRTL C