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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | Operations Management / Process Analysis |
| EmploymentType | Full-time |
GLOBALFOUNDRIESis a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world s most inspired technology companies. With a global manufacturing footprint spanning three continents, GLOBALFOUNDRIES makes possible the technologies and systems that transform industries and give customers the power to shape their markets. GLOBALFOUNDRIES is owned by Mubadala Investment Company. For more information, visit www.globalfoundries.com.Position Title: Test chip design InternWork Area:Foundry IP DevelopmentLocation: BangaloreSummary of Role:. Test chip circuit design, Simulation/Layout/Verification. Develop robust flow and methodology for various Test chip architectures. Good understanding on the Chip level Design aspects and signoff requirements.. Having bond knowledge of package, bond diagram is added advantage., *Required Qualifications: Requires a ME/MS/MTECH in VLSI, Microelectronics from an accredited university.Should be fluent with Cadence EDA tools for schematic and physical layout, design rule checking (DRC), layout versus schematic checking (LVS, schematic and layout extraction, methodology checking)Should be fluent with schematic design/ simulations/verificationsLanguage Fluency Fluent in English Language written & verbal.Must have proficient knowledge of and experience with UNIX environmentMust have hands-on experience with TCL or any other programming languageShould have excellent problem solving skills, written & oral communication, teaming & interpersonal skillsPerform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programsPreferred Qualifications:Knowledge of scripting languages like Python/Perl preferred. Having knowledge on CAD setup and resolution of minor CAD issues
Keyskills :
design rule checkinglayout versus schematiccontinuous improvement facilitationeda toolschip designlevel designcircuit designproblem solvingenglish languagedesign rule checking drc