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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | BPO / Call Center |
| Functional Area | General / Other Software,Engineering Design / Construction |
| EmploymentType | Full-time |
Worked on SOC level test bench and verification environmentTestbench architecture, coding and good understanding of design issues in RTLTest bench generation, test vector creation, simulations, gate level simulationsHands on with System Verilog and Assertion based verification methodologyAt least 3years of experience on HVL (System Verilog, Vera, Specman, E, VMM, OVM, UVM)Should be able to work independently and able to guide other team membersShould have lead a team of 5 or more engineers for at least 1-2 yrsShould have experience with Verilog and popular EDA simulation, SV assertions & test bench methodologies.Experience in developing complex test bench in System Verilog using OVM/UVM methodologyWorked on protocols like AMBA AHB/AXI, MIPI, PCI Express, SATA, USB3, USB2& Ethernet.Experience on formal verificationExcellent written and oral communication skills are necessary.,
Keyskills :
computer programmingsystem verilogarchitecturesimulationsocuvmverilogovmvmmeda