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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Telecom / ISP |
Functional Area | Service / Installation / Repair |
EmploymentType | Full-time |
Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results.It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the extra mile to achieve unthinkable results.It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world. If you have this type of passion, we invite you to take a look at the opportunities available to come join our team.ROLE:This person will be part of next generation Graphics SoC DFT team. Requires strong hands-on knowledge of all facets of the IC design process and good understanding of Design For TestKEY RESPONSIBILITIES:Implementation and verification of DFT architecture and featuresScan/Jtag/boundary scan insertion and ATPG pattern generationMemory BIST logic generation, implementation and verificationATPG patterns verification with gate level simulationTest coverage and test cost reduction analysisPost silicon support to ensure successful bringup and enhance yield learningSkills required:Minimum 8 years working experience in ASIC DFT area.Understanding of Design For Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, scan, memory BIST,etc)Experience with Mentor testkompress and/or Synopsys Tetramax/DFTMAXExperience with VCS simulation tool, Perl/Shell scripting and Verilog RTL designExcellent oral, written and interpersonal communication skills,
Keyskills :
ic designchanging the world caddrafting test methodologiesmodeling cost reductionscan insertion