PE , CAD Engineering

Job Description

Overview This R&D engineering position will be responsible for interfacing to our silicon foundries and technically supporting design teams across the company working on product and IP development. Activities will include initial engagement on new nodes and developing comparative technology assessments , downloading and making available PDKs and EDA support files to CAD and design teams , providing design team support on DRC , ERC , DFM , ESD , and reliability rules and calculators , securing foundry provided IP and seeking 3 rd party IP to fill any gaps , seeking answers when documentation or data is missing , seeking waivers when necessary and elucidating the risks , validating spice model and extraction setups and providing power , performance , area evaluations , coordinating mock and full tapeouts to foundry and being accountable for quality of delivery and checks , facilitating mask reviews , communicating foundry roadmaps and identifying foundry and node choices early in the product definition. This individual contributor will report to the Director of CAD and work closely with a broad set of design and functional teams including CAD engineers , design leads and engineers , and the operations team to consult on post - silicon issues. The position will require direct interaction with external foundry engineers and third - party design IP companies.We are looking for an experienced technologist who can provide excellent and timely process , design rule manual , spice model , and PDK support to ensure internal projects and tapeouts remain on track and achieve their quality and performance goals. The candidate should be able to lead process roadmap , evaluation , and decision - making efforts. The candidate must be able to form symbiotic relationships with design engineering to seamlessly execute to the product roadmap. The candidate will need to have outstanding organization , communication , teamwork , and negotiating skills to ensure the teams are enabled for efficient and accurate execution on multiple product lines , simultaneously. Finally , the individual must be able to support and grow a strong and collaborative relationship with our foundries.ResponsibilitiesExperience working with and taping out to multiple foundries and multiple technology nodes as designer or foundry interface; experience specifically with making MPW or special TO reservations , submitting TO forms and database , resolving all TO issues , and shepherding through final release is highly desired Knowledge and understanding of design rule manuals , pcells , DRC rules , DRC / ERC checking tools , EM rules , EMIR setup and checking tools , ESD / LU rules , and foundry provided process data; experience with RC extraction and ESD checking tools a plus Good understanding of silicon technology (IDM or foundry) with exposure to advanced node process design kits , 7 / 10nm experience is preferred. Familiarity with schematic / layout capture , simulations and DRC / LVS using industry standard EDA tools is highly desirable along with EDA toolset knowledge (across vendors) as they relate to PDK usage. Experience setting up simulation corners , correlating to silicon , and resolving mismatches with design and foundry Proven ability to collect IP requirements from design team (e.g. standard cells , memories , OTP , IOs) and seek foundry based or 3 rd based solutions and required collateral Prior node and foundry selection experience through comparative analysis and assessment Experience working with design team to finalize sign - off conditions for static timing analysis , EM , ESD structures , and full chip ESD robustness. Direct experience with helping to setup and validate digital flows (technology files , synthesis , place and route , extraction , STA sign - off) highly desired Track record of being pro - active , problem solving independently , multi - tasking , and maintaining a high level of responsiveness and accountability Positive , winning attitude and excellent communication skills Overall , must have the technical and interpersonal skills to effectively work with foundries / ASIC - partners , as well as with internal design , CAD and packaging engineers. Works effectively in a multi - site , multi - cultural environment. Self - motivated team player with strong organizational , time management and communication skills. QualificationsQualifications MSEE or equivalent technical degree with semiconductor device physics coursework 2 years experience in a position like this one interfacing directly with major foundries (such as TSMC) and managing the relationship 7 years experience in semiconductor or process design,

Keyskills :
autocad cad autocad drafting drawing statictiminganalysis rcextraction processdesign problemsolving timemanagement timinganalysis negotiation ntegrateddevelopmentenvironments edatools designengineering