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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | Manufacturing |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Duties: Develop micro - architecture and RTL design for digital components for memory and serdes PHY IPs Generating soft - macros (RTL) to be used in test - chip / product designs Setup and analysis of lint , synthesis , timing closure and DFT reports Support Customer integration activities QualificationsSkills / Qualifications: Electrical / Electronic Engineering with at least 8 to 12 years of experience in Logic design , Micro architecture definition Experience working with multiple clock domains , high speed designs Experience with synthesis flow , hands on timing closure , ECO iterations Knowledge of memory (DDRx / HBM / GDDRx) , serdes technology such as - PCI Express , Ethernet , USB is a plus Experience working in a multi - site environment,
Keyskills :
cadencecontrollingdiagnosticsfftgsmrtldesignphydftrtlipspciecolintdesignmacrosserdesogicdesigntimingclosureusbtiming