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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | Manufacturing |
| Functional Area | Engineering Design / Construction |
| EmploymentType | Full-time |
NXP SemiconductorsN.V. (NASDAQ: NXPI) enables secure connections for a smarter world, advancing solutions that make lives easier, better, and safer. As the world leader in secure connectivity solutions for embedded applications, NXP is driving innovation in the automotive, industrial & IoT, mobile, and communication infrastructure markets. Built on more than 60 years of combined experience and expertise, the company has approximately 29,000 employees in more than 30 countries and posted revenue of $8.61 billion in 2020.Person with strong fundamentals and full P&R knowhow and specific leadership in Physical Validaiton tasks. Person who can potentially be a physical design lead for SoC.3 years Experience in Timing Constraints, Lint, Synthesis, Logic Equivalence, Low Power Checks and STA Timing Signoff.Strong Expertise on Developing Timing Constraints, IO Interface constraints.Hands on experience on various flows of synthesis, synchronous & asynchronous design, DDR, Flash Controller, Serial Interfaces, etc.Exposure to low power intent specification development (CPF or UPF).Must have worked on low power flows and Logic Equivalence Signoff.Must have independently handled timing sign-off of both block level and top level.Good understanding of Design Planning, Place & Route and Power Concepts.Must have worked on lower technology nodes such as 16nm, 5nm etc.Hands on experience of Synopsys RTL2GDSII flow tools.Strong working knowledge of TCL for the development of flows and reportingStrong problem solving and multi-tasking skills. Should be able to run multiple experiments focusing on various PPA targets.,
Keyskills :
floor planningdrcroutingverificationphysical designproblem solvingiotstaddrppanxplintflashdesignmobileplacerouteconnectivity solutionstcl