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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | IT - Software |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Job ID: JR0186344Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HirePhysical Design EngineerJob DescriptionCreates bottomsup elements of chip design including but not limited to FET, cell, and blocklevel custom layouts, FUBlevel floor plans, abstract view generation, RC extraction and schematictolayout verification and debug using phases of physical design development including parasitic extraction, static timing, wire load models, clock generation, customer polygon editing, autoplace and route algorithms, floor planning, fullchip assembly, packaging, and verification. Troubleshoots a wide variety up to and including difficult design issues and applied proactive intervention. Schedules, staffs, executes and verifies complex chips development and execution of project methodologies and/or flow developments. Requires expansive knowledge and practical application of methodologies and physical design.QualificationsBE, with 3-6 Yrs of Experience doing Analog IPs like Serdes, PLL, PCIe, Display Port, DDR, USB. Handles block layout independently ensuring quality schedule of deliverables No supervision by lead Works with lead on full chip layout floor plan power grid templates etcGood understanding of RV ESD RoutingKnows all flows and tools like Virtuoso, ICV, Calibre, Redhawk, Totem, Extraction tools.Works with DE to identify tasks does planning and scheduling of the deliverablesInside this Business GroupIP Engineering Groups (IPG) vision Build IPs that power Intels leadership products and power our customers silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intels silicon design process. IPGs guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0186344BangaloreIP Engineering Group (IPG),
Keyskills :
floor planningdrcroutingverificationintegrated development environmentschip designfloor plansrc extractionphysical designstatements of work sow