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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Rs 14 - 30 Lakh/Yr |
Industry | IT - Software |
Functional Area | General / Other Software |
EmploymentType | Full-time |
The candidate will participate in the physical design aspects of the cores, including floor planning, placement, clock tree synthesis, routing, and ECO timing closure. Strong knowledge and experience in Physical Design of IP blocks and/or full chips. Strong hands-on Experience in various aspects of Physical Design flow Floor planning, Placement, CTS, Route, timing analysis and eco flows. 16FF/10FF/7FF Technologies exp must. Strong knowledge of PD tools like Synopsys ICC (II) and/or Cadence Innovus required. Knowledge and exposure to STA (primetime), EMIR analysis, DRC/LVS analysis and fixing desired.Salary: INR 15,00,000 - 30,00,000 PA.Industry: IT-Software / Software ServicesFunctional Area: IT Software - Application Programming, MaintenanceRole Category: Programming & DesignRole: Team Lead/Technical LeadEmployment Type: Full Time, Permanent ,
Keyskills :
planning drc routing verification ip clocktreesynthesis designflow physicaldesign timinganalysis applicationprogramming it sta eco icc design timing cadence software planning analysis lo