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| Job Location | Bangalore |
| Education | Not Mentioned |
| Salary | Not Disclosed |
| Industry | IT - Software |
| Functional Area | General / Other Software |
| EmploymentType | Full-time |
Physical Design Engineer Position : Physical Design Engineer Experience : 2 - 7 Years Education : B.Tech/ BE/ ME/ M.Tech Job Location : Bangalore / Chennai / Hyderabad / Noida Desired Skills : Include all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with Front End Design team to resolve Design Issues Responsibilities: Must possess hands on experience in P&R; from RTL to GDS including timing closure and Physical verification. Design experience in all aspects of physical design. Proficient and powerful user of Synopsys DC, Cadence SOC Encounter. Experience in Mentor Calibre tools to run Physical verification Experience in Apache to run EM IR- analysis is a Plus. Experience in Tcl/ Tk, PERL, Makefile is a Plus Excellent verbal and written communication skill is required. Excellent interpersonal and analytical skills with an ability to work independently and within a team are required. Highly motivated, excellent team player, and customer oriented Apply Position : Physical Design Engineer Experience : 2 - 7 Years Education : B.Tech/ BE/ ME/ M.Tech Job Location : Bangalore / Chennai / Hyderabad / Noida Desired Skills : Include all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out. Should be able to interface with Front End Design team to resolve Design Issues Responsibilities: Must possess hands on experience in P&R; from RTL to GDS including timing closure and Physical verification. Design experience in all aspects of physical design. Proficient and powerful user of Synopsys DC, Cadence SOC Encounter. Experience in Mentor Calibre tools to run Physical verification Experience in Apache to run EM IR- analysis is a Plus. Experience in Tcl/ Tk, PERL, Makefile is a Plus Excellent verbal and written communication skill is required. Excellent interpersonal and analytical skills with an ability to work independently and within a team are required.,
Keyskills :
planning drc routing verification ip frontenddesign clocktreesynthesis frontend timingclosure physicaldesign guidevelopment signalintegrity analyticalskills clockdistribution physicalverification lo