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Job Location | Bangalore |
Education | Not Mentioned |
Salary | Not Disclosed |
Industry | IT - Software |
Functional Area | General / Other Software |
EmploymentType | Full-time |
Proven experience in top level floorplanning/block partitioning, Power planning, understanding and planning of clock mesh structure/conventional CTS, Blockintegration (Including analog IP integration) and Physical Verification Signoff. Engineer should have experience in handling chips of GHz clock frequency range & multi-million instance, and designed complex chips in lower technology nodes (16nm and below). Padframe/BGA planning/design, including RDL routing is required.,
Keyskills :
physical verificationrdlmeshdesignroutingplanningHerculesParasitic ExtractionClock Tree SynthesisVirtuosoDesign Rule CheckingRC ExtractionLayout Versus SchematicFloorplanningMultiprotocol Label SwitchingSession Initiation ProtocolEthern