Post-Si SoC Functional Validation - Power Management Specialist

Job Description

Job ID: JR0139283Job Category: EngineeringPrimary Location: Bangalore, KA INOther Locations:Job Type: Experienced HirePost-Si SoC Functional Validation - Power Management SpecialistJob DescriptionIn this position, the Power Management Validation/debug Lead will serve as a key technical expert in driving Validation, Debug readiness for Power-on and Post-Silicon Validation for all Reset flows, functional power management features and concurrency. Power management technical lead will be working in a cross functional team to develop validation and debug strategies for post-silicon coverage, including shift left pre-silicon efforts. Expected to work closely with IP/SOC design engineers/architects in developing Reset and PM test plan, Validation tools, Validation content and coverage methods. Will drive end to end Reset and PM validation, debug across IP, SoC and platform teams. Uses and applies emulation and platform level tools and techniques to ensure performance to spec. Understands System with HW/FW/SW components as a whole, drives test execution and debug with cross functional teams. Acts as a technical mentor to rest of the team and enables the team deliver results in a fast paced dynamic environment.Qualifications Bachelors/Masters in Hardware Engineering or Electrical/Electronic Engineering or Computer Engineering or Computer Science with 8- 15 years of experience Candidate Must have high degree of Hardware architecture/ microarchitecture experience in CPU/SoC/Chipset/and some of the subsystems areas given below Deep knowledge and skills of Intel IA (IA32 architecture with uArch debug knowledge of Intels Core and Uncore or equivalent architecture.) Good programming skills in C/C++/Python Hands on work in finding bugs in post silicon through fine tuned content Good understanding of various idle and execution time power management features, thermal management features Good understanding Power management IA Core & package states, System power states, dynamic voltage-frequency scaling features, clock and power gating, PCIe device power states includes link power management of PCIe, DDR4, Storage devices, Network devices and BIOS; Expertise in SOC level flows for system power states etc. Good understanding with DFd and drove new debug hooks into Platform/SOC/IP Experience in validating intelligent microcontroller based power control unit Solid understanding of the Validation and Debug flows of a complex CPU Silicon Ability to work well on a team, but also self-driven Hands-On experience of complex SoC sightings and exposure to running cross-site Task forces Knowledge on Debug Tools for JTAG, on chip trace features and ability to debug via OSC/LAs etc; Usage of any Post-Si debug tools (e.g., logic analyzers, oscilloscopes, things like ChipScope on FPGAs, etc.) Knowledge of ARM PM concepts (e.g., P/Q-channel) is a plus Pre-silicon Design / Validation knowledge is a value add. Passionate to find bugs, triage, debug and drive resolution of failures to HW, silicon firmware bugs. Excellent written and oral communications and experience working in a cross functional and cross site team environment are essential. Ability to interact directly with customers and multiple levels of management is a must. Inside this Business GroupThe Silicon Engineering Group is a worldwide organization focused on the development and integration of SOCs, Cores, and critical IPs that power Intel s leadership products. This business group leverages an incomparable mix of experts with different backgrounds, cultures, perspectives, and experiences to unleash the most innovative, amazing, and exciting computing experiences.Legal Disclaimer:Intel prohibits discrimination based on race, color, religion, gender, national origin, age, disability, veteran status, marital status, pregnancy, gender expression or identity, sexual orientation or any other legally protected status.It has come to our notice that some people have received fake job interview letters ostensibly issued by Intel, inviting them to attend interviews in Intel s offices for various positions and further requiring them to deposit money to be eligible for the interviews. We wish to bring to your notice that these letters are not issued by Intel or any of its authorized representatives. Hiring at Intel is based purely on merit and Intel does not ask or require candidates to deposit any money. We would urge people interested in working for Intel, to apply directly at www.jobs.intel.com and not fall prey to unscrupulous elements.INExperienced HireJR0139283Bangalore,

Keyskills :
teachingsurgerytheatreptsadministrationpower controltest executionnetwork devicesstorage devicescomputer sciencepower managementthermal management